*Please be advised that the poster needs to be displayed by being attached for both days.
| No. | IDX | PAPER_NUM | S_TYPE | S_TOPIC | S_TITLE |
|---|---|---|---|---|---|
| 1 | 1008 | 01_1008 | Poster | 1 | Low-Thermal-Budget (≤ 350 ̊ C) IGZO Ferroelectric Hf0.5Zr0.5O2 Field-Effect Transistors with Large Memory Window |
| 2 | 1027 | 01_1027 | Poster | 1 | High Charge Trapping Density in Remote Plasma ALD ZrO2 Thin Films for Nonvolatile Memory Applications |
| 3 | 1003 | 02_1003 | Poster | 2 | Nanoprobe Based Information Processing: Nanoprobe-MRAM |
| 4 | 1012 | 02_1012 | Poster | 2 | Demonstration of the High Performance SOT-MRAM Chip |
| 5 | 1014 | 02_1014 | Poster | 2 | A Novel Radiation-Hardened Non-volatile Magnetic Latch Circuit |
| 6 | 1017 | 02_1017 | Poster | 2 | High Resistance and Low Variation 8Kb SOT-MRAM Compute-in-Memory Array based on 1T-1R Cell Structure |
| 7 | 1016 | 03_1016 | Poster | 3 | Self-Aligned Atomically Thin Thermal Barrier for Highly Energy-Efficient Phase-Change Memory |
| 8 | 1018 | 03_1018 | Poster | 3 | Cryogenic Phas Change Memory |
| 9 | 1019 | 03_1019 | Poster | 3 | Improved Reliability of Extreme High Unbalanced Magnetron Sputtered Ge2Sb2Te5 Thin Film-Based Phase Change Memory by Controlling Post Annealing Time |
| 10 | 1032 | 03_1032 | Poster | 3 | Engineering Thermoelectric Effect in Phase Change Heterostructure by Layered MoS2 for High-Performance, Highdensity Phase Change Memory |
| 11 | 1036 | 03_1036 | Poster | 3 | High-Performance Selector-Only Memory Devices based on Si-Doped GeS Materials |
| 12 | 1059 | 03_1059 | Poster | 3 | Ultra-High Stability and Set Operation Performance in GeTe/Sb2Te3 Superlattices Using Minimized Density Change |
| 13 | 1004 | 04_1004 | Poster | 4 | Impact of Memory Parameters on Sensitivity Margin of Analog-to-Digital Converter Limiting Neural Network Density |
| 14 | 1010 | 04_1010 | Poster | 4 | Controllable Biodegradation of Flexible Resistive Switching Device with Quantized Conductance Characteristics |
| 15 | 1025 | 04_1025 | Poster | 4 | Area Efficient Multi-Memristor Bit Cell Design for Resistive Processing Unit-Based Neural Network Training |
| 16 | 1026 | 04_1026 | Poster | 4 | In-memory Cryptographic Engine with Dual-Polarity Memristive Crossbar Array |
| 17 | 1028 | 04_1028 | Poster | 4 | Concealable Physical Unclonable Function Generation and In-Memory Encryption Machine based on Vertical Self-Rectifying Memristors |
| 18 | 1029 | 04_1029 | Poster | 4 | Cyclic Plasma Treatment for Enhancing Performance of Bulk-Conductive Resistive Switching Memory |
| 19 | 1033 | 04_1033 | Poster | 4 | Investigating Thermal Accumulation Effects in ReRAM Devices at Sub-100 ps Timescales with Variable Delays |
| 20 | 1005 | 05_1005 | Poster | 5 | Polarization Dependent Oxygen Vacancy Distribution in Ferroelectric Hf0.5Zr0.5O2 Capacitors |
| 21 | 1011 | 05_1011 | Poster | 5 | Integration of Superlattices and Novel Co-Doped (Hf,Zr)O2 Ferroelectric Films into BEoL for Enhanced FeMFET Performance |
| 22 | 1023 | 05_1023 | Poster | 5 | Ferroelectric FETs as embedded NVRAM supporting Cryogenic Quantum Processors |
| 23 | 1038 | 05_1038 | Poster | 5 | Enhancement of Electrical Properties in (Hf,Zr)O2 Ferroelectric Thin Films via Co-Plasma ALD Method |
| 24 | 1055 | 05_1055 | Poster | 5 | Effect of Tungsten Insertion Layer on the Characteristics of TiN/Co-PEALD HZO/TiN Ferroelectric Capacitor |
| 25 | 1015 | 06_1015 | Poster | 6 | Development of Scaling for ULTRARAM Memory |
| 26 | 1030 | 06_1030 | Poster | 6 | Optimizing the Performance of the Atomic-Layer-Deposited Zinc-Tin-Oxide Thin Film Transistor by Ozone Treatment and Thermal Annealing |
| 27 | 1034 | 06_1034 | Poster | 6 | Improving Electrical Performances of Amorphous Zn-Sn-O Thin-Film Transistor through Al Doping for Next-Generation DRAM Channel Materials |
| 28 | 1009 | 07_1009 | Poster | 7 | Disordered Configurable Elemental Chalcogen in the Joule Heating Device |
| 29 | 1022 | 07_1022 | Poster | 7 | Study of Performance and Structural Effects in Vertical Selector-Only Memory |
| 30 | 1039 | 07_1039 | Poster | 7 | Atomic Layer Deposition of Sn-Doped GeSe2 for As-Free Ovonic Threshold Switch with Low Off-Current |
| 31 | 1057 | 07_1057 | Poster | 7 | Transient Delocalization in Ovonic Threshold Switch Material |
| 32 | 1020 | 08_1020 | Poster | 8 | Phase Change Memristors with Titanium Confinement Layers for Efficient Synaptic Devices |
| 33 | 1037 | 08_1037 | Poster | 8 | Synaptic Weight Update Characteristics of Phase Change Memory with Different Top Electrodes Diameter |
| 34 | 1040 | 08_1040 | Poster | 8 | Implementation of Bayesian Network and Bayesian Inference using Cu0.1Te0.9/HfO2/Pt Threshold Switching Memristor |
